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1.0
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Features
2.0
Description
On-chip tunable voltage-controlled crystal oscillator circuitry (VCXO) allows precise system frequency tuning (pull range typically 300ppm) VCXO tuning range: 0-3V Uses inexpensive fundamental-mode crystals Integrated phase-locked loop (PLL) multiplies VCXO frequency to the higher system frequencies needed 5V supply voltage (contact factory for 3.3V) Small circuit board footprint (8-pin 0.150 SOIC) Custom frequency selections available - contact your local AMI Sales Representative for more information
* * * * * *
The FS6127 is a monolithic CMOS clock generator IC designed to minimize cost and component count in digital video/audio systems. At the core of the FS6127 is circuitry that implements a voltage-controlled crystal oscillator when an external resonator (nominally 13.5MHz) is attached. The VCXO allows device frequencies to be precisely adjusted for use in systems that have frequency matching requirements, such as digital satellite receivers. A high-resolution phase-locked loop generates the output clock frequency (CLK). The CLK frequency is phaselocked and frequency-locked to the VCXO frequency.
Figure 1: Pin Configuration
XIN VDD XTUNE VSS
1 8
Table 1: Crystal / Output Frequencies
XOUT VSS VDD CLK
NOTE: Contact AMI for custom PLL frequencies and 3.3 volt versions
DEVICE FS6127-01
fXIN (MHz) 13.5
CLK (MHz) 27
FS6127
2 3 4
7 6 5
8-pin (0.150) SOIC
Figure 2: Block Diagram
XIN VCXO XOUT XTUNE PLL CLK
FS6127
This document contains information on a new product. Specifications and information herein are subject to change without notice.
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Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input, DO = Digital Output; P = Power/Ground; # = Active Low pin
PIN 1 2 3 4 5 6 7 8
TYPE AI P AI P DO P P AO
NAME XIN VDD XTUNE VSS CLK VDD VSS XOUT VCXO Crystal Feedback Power Supply (+5V) VCXO Tune Ground Clock Output Power Supply (+5V) Ground VCXO Crystal Drive
DESCRIPTION
3.0
3.1
Functional Block Description
Phase-Locked Loop (PLL)
The on-chip PLL is a standard frequency- and phaselocked loop architecture. The PLL multiplies the reference oscillator to the desired frequency by a ratio of integers. The frequency multiplication is exact with a zero synthesis error.
the oscillator circuit. The actual amount that changing the load capacitance alters the oscillator frequency will be dependent on the characteristics of the crystal as well as the oscillator circuit itself. Specifically, the motional capacitance of the crystal (usually referred to by crystal manufacturers as C1), the static capacitance of the crystal (C0), and the load capacitance (CL) of the oscillator determine the "warping" or "pulling" capability of the crystal in the oscillator circuit. A simple formula to obtain the warping capability of a crystal oscillator is:
3.2
Voltage-Controlled Crystal Oscillator (VCXO)
f ( ppm) =
The VCXO provides a tunable, low-jitter frequency reference for the rest of the FS6127 system components. Loading capacitance for the crystal is internal to the FS6127. No external components (other than the crystal resonator itself) are required for operation of the VCXO. Continuous fine-tuning of the VCXO frequency is accomplished by varying the voltage on the XTUNE pin. The total change (from one extreme to the other) in effective loading capacitance is t.b.d. nominal. The oscillator operates the crystal resonator in the parallel-resonant mode. Crystal warping, or the "pulling" of the crystal oscillation frequency, is accomplished by altering the effective load capacitance presented to the crystal by
6 C1 x (C L 2 - C L1)x 10 2 x (C 0 + C L 2 )x (C 0 + C L1)
where CL1 and CL2 are the two extremes of the applied load capacitance. EXAMPLE: A crystal with the following parameters is used. With C1 = 0.02pF, C0 = 5pF, CL1 = 10pF, and CL2 = 22.66pF, the tuning range is
f =
0.02 x (22.66 - 10)x 10 6 = 305 ppm . 2 x (5 + 22.66 )x (5 + 10 )
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Electrical Specifications
Table 3: Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance, functionality, and reliability.
PARAMETER Supply Voltage (VSS = ground) Input Voltage, dc Output Voltage, dc Input Clamp Current, dc (VI < 0 or VI > VDD) Output Clamp Current, dc (VI < 0 or VI > VDD) Storage Temperature Range (non-condensing) Ambient Temperature Range, Under Bias Junction Temperature Lead Temperature (soldering, 10s) Input Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7)
SYMBOL VDD VI VO IIK IOK TS TA TJ
MIN. VSS-0.5 VSS-0.5 VSS-0.5 -50 -50 -65 -55
MAX. 7 VDD+0.5 VDD+0.5 50 50 150 125 125 260 2
UNITS V V V mA mA C C C C kV
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy electrostatic discharge.
Table 4: Operating Conditions
PARAMETER Supply Voltage Ambient Operating Temperature Range SYMBOL VDD TA CONDITIONS/DESCRIPTION 5V 10% MIN. 4.75 0 TYP. 5 MAX. 5.25 70 UNITS V C
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Unless otherwise stated, VDD = 5V 10%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are 3 from typical. Negative currents indicate current flows out of the device.
PARAMETER Overall Supply Current, Dynamic, with Loaded Outputs Voltage Controlled Crystal Oscillator Crystal Resonator Frequency Crystal Loading Capacitance Crystal Resonator Motional Capacitance VCXO Tuning Range VCXO Tuning Characteristic Crystal Drive Level Clock Output (CLK) High-Level Output Source Current * Low-Level Output Sink Current * Output Impedance * Short Circuit Source Current * Short Circuit Sink Current *
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
IDD
fXTAL = 13.5MHz; CL = 10pF
20
mA
fXTAL CL(xtal) C1(xtal)
Fundamental Mode As seen by a crystal connected to XIN and XOUT (@ VXTUNE = 1.65V) AT cut fXTAL = 13.5MHz; CL = 14pF; CMOT = 25fF Note: positive F for positive V RXTAL=20 ohm; CL = 14pF
10
13.5 14 25 300 100 200
15
MHz pF fF ppm ppm/V uW
IOH IOL zOH zOL IOSH IOSL
VO = 2.0V VO = 0.4V VO = 0.1VDD; output driving high VO = 0.1VDD; output driving low VO = 0V; shorted for 30s, max. VO = 5V; shorted for 30s, max.
mA mA mA mA
Table 6: AC Timing Specifications
Unless otherwise stated, VDD = 5V 10%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are 3 from typical.
PARAMETER Clock Outputs (CLKx) Duty Cycle * Jitter, Absolute Period (pk-pk) * Jitter, RMS Long Term (y()) * Rise Time * Fall Time * Output Frequency Synthesis Error VCXO Stabilization Time * PLL Stabilization Time *
SYMBOL
CONDITIONS/DESCRIPTION
CLOCK (MHz)
MIN.
TYP.
MAX.
UNITS
thi / tclk; Measured at VDD/2 tj(P) tj(LT) tr tf tVCXOSTB tPLLSTB From rising edge to next rising edge at VDD/2, CL = 10pF From 0-500s at VDD/2, CL = 10pF compared to ideal clock source VDD = 5V; VO = 0.5V to 4.5V; CL = 10pF VDD = 5V; VO = 4.5V to 0.5V; CL = 10pF (unless otherwise noted in Frequency Table) From power valid From VCXO stable
45 300 150
55
% ps ps ns ns
0 10 500
ppm ms us
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Package Information
Table 7: 8-pin SOIC (0.150") Package Dimensions
DIMENSIONS INCHES MIN. A A1 A2 B C D E e H h L 0.061 0.004 0.055 0.013 0.0075 0.189 0.150 0.230 0.010 0.016 0 MAX. 0.068 0.0098 0.061 0.019 0.0098 0.196 0.157 0.244 0.016 0.035 8 MILLIMETERS MIN. 1.55 0.102 1.40 0.33 0.191 4.80 3.81 5.84 0.25 0.41 0 MAX. 1.73 0.249 1.55 0.49 0.249 4.98 3.99 6.20 0.41 0.89 8
BASE PLANE 1 ALL RADII: 0.005" TO 0.01"
R
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AE"CAAC"#)#$E#AC
h x 45 B e A2 A D A1
SEATING PLANE
7 typ.
0.050 BSC
1.27 BSC
C L
Table 8: 8-pin SOIC (0.150") Package Characteristics
PARAMETER Thermal Impedance, Junction to Free-Air 8-pin 0.150" SOIC Lead Inductance, Self Lead Inductance, Mutual Lead Capacitance, Bulk SYMBOL JA L11 L12 C11 CONDITIONS/DESCRIPTION Air flow = 0 m/s Corner lead Center lead Any lead to any adjacent lead Any lead to VSS TYP. 110 2.0 1.6 0.4 0.27 UNITS C/W nH nH pF
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Ordering Information
DEVICE NUMBER PACKAGE TYPE 8-pin (0.150") SOIC (Small Outline Package) 8-pin (0.150") SOIC (Small Outline Package) OPERATING TEMPERATURE RANGE 0C to 70C (Commercial) 0C to 70C (Commercial) SHIPPING CONFIGURATION Tape and Reel Tubes
ORDERING CODE
11640-803 11640-813
FS6127-01 FS6127-01
Copyright (c) 1998 American Microsystems, Inc.
Devices sold by AMI are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMI makes no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. AMI makes no warranty of merchantability or fitness for any purposes. AMI reserves the right to discontinue production and change specifications and prices at any time and without notice. AMI's products are intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recommended without additional processing by AMI for such applications.
American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796, WWW Address: http://www.amis.com E-mail: tgp@amis.com
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